Author: Jerry McGoveran

Rescue Your Tape Out From False Path Timing Violations

Gate level simulation (GLS) can be a lengthy and tedious undertaking.  Tests can take hours or days in GLS with full timing values annotated.  With a debug loop measured in…
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Optimizing Simulation Run Times With Checkpoints

Gate level simulation (GLS) tests with full timing (SDF annotation) take hours, days or even weeks to run. Even RTL simulations for such things as performance modeling, power estimation or…
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Gate Level Simulation: A Comprehensive View

Your manager has decided that post-layout netlist verification using gate level simulation (GLS) will be a gating task on your chip design project, and has assigned you to accomplish it.…
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