Logic Design

Certus consultants have broad experience in RTL design techniques using the latest HDL standards including SystemVerilog (IEEE-1800), Verilog, C/C++.  We can provide front end design, microarchitecture specification, chip partitioning advice, and conduct design reviews.


We have expertise in the latest high level, coverage based, and constrained random verification methodologies, utilizing SystemVerilog, UVM, and C/C++ languages.  We can build a testbench for you, or enhance your existing one.  We have helped verify some of the most complex SoCs in the industry, from a 10M gate Broadband system, to a 100M gate GPU, to a 600M gate parallel processing monster.

Staying On The Cutting Edge

As new tools and standards are developed, we strive to keep ourselves and our clients educated on the latest productivity tools and techniques.  The newly emerging Portable Stimulus Standard is one such example.  As this standard nears adoption, you can expect Certus consultants to be among the early experts, helping our clients implement this exciting new approach to verification.

Need Help?

If your project is keeping you up at night, give us a call or send us an email.  We'll be happy to discuss ways that we can help!